(errno = ENOENT) # Loading work.rs_latch # ** Error: (vsim-19) Failed to access library 'cyclonev_ver' at "cyclonev_ver". (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_lnsim_ver' at "altera_lnsim_ver". (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'sgate_ver' at "sgate_ver". (errno = ENOENT) # ** Error: (vsim-19) Failed to access library '220model_ver' at "220model_ver". (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_mf_ver' at "altera_mf_ver". (errno = ENOENT) # ** Error: (vsim-19) Failed to access library 'altera_ver' at "altera_ver".
# Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 # - Compiling module rs_latch # Top level modules: # rs_latch # Model Technology ModelSim ALTERA vlog 10.1e Compiler 2013.06 # - Compiling module rs_latch_vlg_sample_tst # - Compiling module rs_latch_vlg_check_tst # - Compiling module rs_latch_vlg_vec_tst # Top level modules: # rs_latch_vlg_vec_tst # vsim -L cyclonev_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver -c -voptargs=\"+acc\" -t 1ps -novopt work.rs_latch_vlg_vec_tst # Loading work.rs_latch_vlg_vec_tst # ** Error: (vsim-19) Failed to access library 'cyclonev_ver' at "cyclonev_ver". **** Running the ModelSim simulation **** C:/altera/14.0/modelsim_ase/win32aloem/vsim -c -do rs_latch.do Reading C:/altera/14.0/modelsim_ase/tcl/vsim/pref.tcl # 10.1e # do rs_latch.do # ** Warning: (vlib-34) Library already exists at "work". do script **** D:/FPGA/Lab03/Part1_RSLatch/simulation/qsim/rs_latch.do generated. Using: C:\altera\14.0\modelsim_ase\win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. (only list part of error message because of the characters number limitation in this forum.) - Determining the location of the ModelSim executable.
ERROR LOADING DESIGN IN MODELSIM SERIES
And when I use "Run Functional Simulation" or "Run Timing Simulation", it would start to run a series processes, and I would get a error message as follows. module rs_latch (Clk, R, S, Q) input Clk, R, S output Q wire R_g, S_g, Qa, Qb and(R_g, R, Clk) and(S_g, S, Clk) nor(Qa, R_g, Qb) nor(Qb, S_g, Qa) assign Q = Qa endmodule - The input setup of RS latch simulation in simulation waveform editor is as attachment.
Hello I am using simulation waveform editor (Altera Quartus II 64-Bit 14.0 Web Edition) to simulate a simple RS latch with verilog as follows.
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